External Memory Interfaces Intel® Arria® 10 FPGA IP User Guide

ID 683106
Date 12/19/2023

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Document Table of Contents Implementing a x8 Interface with Hard Memory Controller

The following diagram illustrates the use of a single I/O bank to implement a DDR3 or DDR4 x8 interface using the hard memory controller.
Figure 5. Single Bank x8 Interface With Hard Controller

In the above diagram, shaded cells indicate resources that are in use.

Note: For information on the I/O lanes and pins in use, consult the pin table for your device or the readme.txt file generated with your IP.