External Memory Interfaces Intel® Arria® 10 FPGA IP User Guide
A newer version of this document is available. Customers should click here to go to the newest version.
Visible to Intel only — GUID: hco1416490786092
Ixiasoft
Visible to Intel only — GUID: hco1416490786092
Ixiasoft
10.3. Pin and Resource Planning
Typically, all external memory interfaces require the following FPGA resources:
- Interface pins
- PLL and clock network
- Other FPGA resources—for example, core fabric logic, and on-chip termination (OCT) calibration blocks
Once all the requirements are known for your external memory interface, you can begin planning your system.