External Memory Interfaces Intel® Arria® 10 FPGA IP User Guide

ID 683106
Date 12/19/2023
Public

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Document Table of Contents

16. Document Revision History for External Memory Interfaces Intel® Arria® 10 FPGA IP User Guide

Document Version Intel® Quartus® Prime Version IP Version Changes
2023.12.19 21.1 19.2.0
  • In the Product Architecture chapter:
    • Added a sentence to the first bullet point in the PLL Reference Clock Networks topic.
    • Added a note about ALERT# placement, to the Using the Ping Pong PHY topic.
  • In the DDR4 chapter, removed reference to a Use clamshell layout parameter from the DDR4 Parameters: General topic.
  • Added additional information to global_reset_n references in the General Guidelines and Resource Sharing Guidelines (Multiple References) topics in each protocol-specific chapter throughout the document.
2023.05.10 21.1 19.2.0 In each protocol-specific Parameter Descriptions section, modified the description of the PLL reference clock jitter parameter.
2023.04.18 21.1 19.2.0 In the DDR4 chapter, removed preload references from the Group: Diagnostics / Simulation Options table in the Intel® Arria® 10 EMIF IP DDR4 Parameters: Diagnostics topic.
2022.09.28 21.1 19.2.0 In the Parameter Description sections of the DDR3, DDR4, QDR II, RLDRAM 3, and LPDDR3 chapters, removed the Groups: Diagnostics / Traffic Generator table, because the parameters described therein are not supported by the Intel® Arria® 10 EMIF IP.
2022.03.11 21.1 19.2.0
  • In the Product Architecture chapter, added content to the Restrictions on I/O Bank Usage for Intel® Arria® 10 EMIF IP with HPS topic.
  • In the DDR4 chapter:
    • In the Layout Guidelines topic, modified the second bullet point in the Clock Routing description in the Layout Guidelines table.
    • In the Length Matching Rules topic, modified the propagation delay value in the SDRAM Component Address and Command Routing Guidelines figure,
2021.12.06 21.1 19.2.0 In the DDR4 chapter:
  • Added alert_n Pin Termination Recommendation topic to the Pin Guidelines section.
  • Modified the Dynamic On-Chip Termination (OCT) in Intel® Arria® 10 Devices topic.
  • Modified the alert_n pin termination guidance in the Length Matching Rules topic in the Board Design Guidelines section.
2021.03.29 21.1 19.2.0
  • In the Simulating Memory IP chapter, removed references to the NCSim* simulator.
  • In the Intel® Arria® 10 EMIF IP DDR4 chapter, added content to the Enable ALERT#/PAR pins description, in the Intel® Arria® 10 EMIF IP DDR4 Parameters: Memory topic.
  • Added Package Migration topic to the Board Design Guidelines section of each protocol-specific chapter.
2020.12.18 19.3 19.1.0 In the Memory Mapped Register (MMR) Tables section of the End-User Signals chapter, added information about ECC errors to the ecc6: Address of Most Recent Correction Command Dropped topic.
2020.04.10 19.3 19.1.0 In the Controller Parameters section of the DDR3 and DDR4 chapters, removed a sentence from the description of the Enable Error Detection and Correction Logic with ECC parameter.
2020.03.12 19.3 19.1.0 Modified the Restrictions on I/O Bank Usage for Intel® Arria® 10 EMIF IP with HPS topic in the Product Architecture topic.
2020.01.28 19.3 19.1.0 Added the x4 DIMM Implementation topic to the Pin and Resource Planning sections of the Intel® Arria® 10 EMIF IP for DDR3 and Intel® Arria® 10 EMIF IP for DDR4 chapters.
2019.09.30 19.3 19.1.0
  • Added the Release Information topic.
  • In the Intel® Arria® 10 EMIF IP for DDR3 chapter, changed the text of the third bullet in step 10, in the General Guidelines topic.
  • In the Intel® Arria® 10 EMIF IP for DDR4 chapter:
    • Added Additional Layout Guidelines for DDR4 Twin-die Devices topic to the DDR4 Board Design Guidelines section.
    • Changed the text of the third bullet in step 10, in the General Guidelines topic.
  • In the Bank Interleaving topic of theController Optimization chapter, made a correction to the material within parentheses in the description of the second supported interleaving option.
  • In the Intel® Arria® 10 EMIF IP Debugging chapter:
    • Restructured the Debugging Intel® Stratix® 10 EMIF IP section.
    • Added the Using the Traffic Generator with the Generated Design Example topic.
2019.04.30 19.1  
  • Modified the PHY Address & Command values for the Quarter:Write and Quarter:Read rows in the Latency in Full-Rate Memory Clock Cycles table in the Latency topic in the Controller Optimization chapter.
  • Added the External Memory Interfaces Intel® Arria® 10 FPGA IP User Guide Archives chapter.
2019.04.01 19.1  
  • Added Slew Rates topic to the Board Design Guidelines section in each of the DDR3, DDR4, QDR II/II+/II+ Xtreme, QDR-IV, and LPDDR3 protocol-specific chapters.
  • Revised the Optimizing Timing topic in the Intel® Stratix® 10 EMIF IP Timing Closure chapter.
2018.10.30 18.1   Changed the recommended input side termination for Data and Data Strobe signals to 120 ohms in the On-Chip Termination Recommendations for Intel® Arria® 10 Devices topic in the Intel® Arria® 10 EMIF IP for DDR3 chapter.
2018.09.24 18.1  
  • Removed local_reset_req and local_reset_status from all protocols in the Interface and Signal Descriptions section of the Intel® Arria® 10 EMIF IP End-User Signals chapter.
  • Removed hps_emif from the QDR II, QDR-IV, RLDRAM 3, and LPDDR3 sections in the Interface and Signal Descriptions section of the Intel® Arria® 10 EMIF IP End-User Signals chapter.
  • Removed mem_reset_n from the description of the mem interface for QDR II and LPDDR3 in the Interface and Signal Descriptions section of the Intel® Arria® 10 EMIF IP End-User Signals chapter.
  • Removed mem_ck and mem_ck_n from the description of the mem interface for QDR II in the Interface and Signal Descriptions section of the Intel® Arria® 10 EMIF IP End-User Signals chapter.
  • Removed a note from the I/O SSM Sharing topic, in the Product Architecture chapter.
  • Added notes to the Bank Management Efficiency and Data Transfer topics in the Optimizing Controller Performance chapter.
  • Modified the names of the interleaving options in the Bank Interleaving topic in the Optimizing Controller Performance chapter.
  • Added Efficiency Monitor and Protocol Checker section to the IP Debugging chapter.
2018.08.08 18.0  
  • In the Command and Address Signals topic in the DDR3 and DDR4 chapters, changed SSTL-12 I/O standard reference to 1.2V I/O standard.
  • Modified the descriptions of the Clock rate of user logic, Memory format, DQ width, and Enable In-System-Sources-and-Probes parameters in the DDR3, DDR4, QDR II/II+/Xtreme, QDR-IV, and RLDRAM 3 chapters, as appropriate.
  • Removed the Traffic Generator 2.0 section from the Intel® Arria® 10 EMIF