External Memory Interfaces Intel® Arria® 10 FPGA IP User Guide

ID 683106
Date 12/19/2023
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Document Table of Contents
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4.1.2.17. emif_usr_clk_sec for DDR4

User clock interface (for the secondary interface in ping-pong configuration)

Table 59.  Interface: emif_usr_clk_secInterface type: Clock Output
Port Name Direction Description
emif_usr_clk_sec Output User clock domain. Intended for the secondary interface in a ping-pong configuration.