External Memory Interfaces Intel® Arria® 10 FPGA IP User Guide

ID 683106
Date 5/10/2023
Public
Document Table of Contents

14.4.1. Signals to Monitor with the Signal Tap II Logic Analyzer

This topic lists the memory controller signals you should consider analyzing for different memory interfaces. This list is not exhaustive, but is a starting point.

Monitor the following signals:

  • amm_addr
  • amm_rdata
  • amm_rdata_valid
  • amm_read_req
  • amm_ready
  • amm_wdata
  • amm_write_req
  • fail
  • pass
  • afi_cal_fail
  • afi_cal_success
  • test_complete
  • be_reg (QDRII only)
  • pnf_per_bit
  • rdata_reg
  • rdata_valid_reg
  • data_out
  • data_in
  • written_data_fifo|data_out
  • usequencer|state *
  • usequencer|phy_seq_rdata_valid
  • usequencer|phy_seq_read_fifo_q
  • usequencer|phy_read_increment_vfifo *
  • usequencer|phy_read_latency_counter
  • uread_datapath|afi_rdata_en
  • uread_datapath|afi_rdata_valid
  • uread_datapath|ddio_phy_dq
  • qvld_wr_address *
  • qvld_rd_address *

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