3.4.3. Efficiency Impact
The exact flow of operations executed by the recalibration engine that affects memory traffic is described below:
- Enter Self-Refresh Mode. The EMIF calibration CPU triggers self-refresh entry on the hard memory controller. The controller flushes all pending operations, precharges all banks and issues the self-refresh command. This operation introduces a delay of approximately 25 Memory clock cycles (precharge all and self-refresh entry commands).
- Confirm Self-Refresh Mode. The EMIF calibration CPU polls the hard memory controller to confirm that the clocks have stopped. This operation introduces no delay.
- Issue codeword update. The EMIF calibration CPU triggers user-mode OCT logic to update code words. This operation introduces a delay of 50-100ns, depending on the device speed grade.
- Allow Exit Self-Refresh Mode. The EMIF calibration CPU enables automatic self-refresh exit logic. This operation introduces a delay of 50-100ns, depending on the device speed grade.
- Wait for Memory Traffic. The hard memory controller waits for an incoming read or write command on the Avalon® bus. The delay introduced by this operation varies, depending on the user application.
- Exit Self Refresh Mode. The hard memory controller issues the Self-Refresh Exit command and a simultaneous memory-side RZQ calibration (ZQCS) command. The delay introduced by this operation varies according to the device speed bin (up to ~1000 memory clock cycles for fastest memory devices).
The efficiency impact on throughput-sensitive work loads is less than one percent, even under worst-case scenarios with all banks active. However, be aware that the first command issued after the hard memory controller exits self-refresh mode will incur the latency overhead of waiting for the memory DLL to re-lock when the Self-Refresh Exit command is issued by the hard memory controller. Contact Intel® FPGA Technical Services for information on how to manually trigger or inhibit periodic OCT updates for applications that are sensitive to latency.
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