External Memory Interfaces Intel® Arria® 10 FPGA IP User Guide

ID 683106
Date 5/10/2023
Public
Document Table of Contents

4.4.26. dramsts

address=59(32 bit)

Field Bit High Bit Low Description Access
phy_cal_success 0 0 This bit is set to 1 if the PHY calibrates successfully. Read
phy_cal_fail 1 1 This bit is set to 1 if the PHY does not calibrate successfully. Read

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