External Memory Interfaces Intel® Arria® 10 FPGA IP User Guide

ID 683106
Date 12/19/2023

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Document Table of Contents QDR IV SRAM Data, DINV, and QVLD Signals

The read data is edge-aligned with the QKA or QKB# clocks while the write data is center-aligned with the DKA and DKB# clocks.
QK is shifted by the DLL so that the clock edges can be used to clock in the DQ at the capture register.
Figure 79. Edge-Aligned DQ and QK Relationship During Read

Figure 80. Center-Aligned DQ and DK Relationship During Write

The polarity of the QKB and QKB# pins in the Intel® FPGA external memory interface IP was swapped with respect to the polarity of the differential input buffer on the FPGA. In other words, the QKB pins on the memory side need to be connected to the negative pins of the input buffers on the FPGA side, and the QKB# pins on the memory side need to be connected to the positive pins of the input buffers on the FPGA side. Notice that the port names at the top-level of the IP already reflect this swap (that is, mem_qkb is assigned to the negative buffer leg, and mem_qkb_n is assigned to the positive buffer leg).

The synchronous read/write input, RWx#, is used in conjunction with the synchronous load input, LDx#, to indicate a Read or Write Operation. For port A, these signals are sampled on the rising edge of CK clock, for port B, these signals are sampled on the falling edge of CK clock.

QDR IV SRAM devices have the ability to invert all data pins to reduce potential simultaneous switching noise, using the Data Inversion Pin for DQ Data Bus, DINVx. This pin indicates whether DQx pins are inverted or not.

To enable the data pin inversion feature, click Configuration Register Settings > Option Control in the parameter editor.

QDR IV SRAM devices also have a QVLD pin which indicates valid read data. The QVLD signal is edge-aligned with QKx or QKx# and is high approximately one-half clock cycle before data is output from the memory.

Note: The Intel® ZFPGA external memory interface IP does not use the QVLD signal.