External Memory Interfaces Intel® Arria® 10 FPGA IP User Guide

ID 683106
Date 5/10/2023
Document Table of Contents cal_debug_clk for DDR3

User calibration debug clock interface

Table 27.  Interface: cal_debug_clkInterface type: Clock Input
Port Name Direction Description
cal_debug_clk Input User clock domain

Did you find the information on this page useful?

Characters remaining:

Feedback Message