External Memory Interfaces Intel® Arria® 10 FPGA IP User Guide

ID 683106
Date 5/10/2023
Document Table of Contents

3.1.1. I/O Subsystem

The I/O subsystem consists of two columns inside the core of the Intel® Arria® 10 device.

Each column can be thought of as loosely analogous to an I/O bank.

Figure 2.  I/O Subsystem

The I/O subsystem provides the following features:

  • General-purpose I/O registers and I/O buffers
  • On-chip termination control (OCT)
  • I/O PLLs for external memory interfaces and user logic
  • Low-voltage differential signaling (LVDS)
  • External memory interface components, as follows:
    • Hard memory controller
    • Hard PHY
    • Hard Nios processor and calibration logic
    • DLL

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