External Memory Interfaces Intel® Arria® 10 FPGA IP User Guide

ID 683106
Date 5/10/2023
Document Table of Contents

12.4.1. Performing Early I/O Timing Analysis

To perform early I/O timing analysis, follow these steps:
  1. Instantiate an EMIF IP core.
    1. On the Memory Timing tab, enter accurate memory parameters.
    2. On the Board Timing tab, enter accurate values for Intersymbol Interference, and Board and Package Skews.
  2. After generating your IP core, create a Intel® Quartus® Prime project and select your device from the Available devices list.
  3. To launch the Timing Analyzer, select Timing Analyzer from the Tools menu.
  4. To run early I/O timing analysis:
    1. Select Run Tcl Script from the Script menu.
    2. Run \ip\ed_synth\ed_synth_emif_a10_0\altera_emif_arch_nf_<variation_name>\synth\<variation_name>_report_io_timing.tcl.

The following figure shows an early I/O timing analysis from the Timing Analyzer using a DDR3 example design.

Figure 107.  Report DDR Timing Results

Report DDR details the read capture, write, address and command, DQS gating, and write leveling timing analyses, which are identical to those obtained after a full design compilation. Core FPGA timing paths are not included in early I/O timing analysis.

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