12.4.1. Performing Early I/O Timing Analysis
- Instantiate an EMIF IP core.
- On the Memory Timing tab, enter accurate memory parameters.
- On the Board Timing tab, enter accurate values for Intersymbol Interference, and Board and Package Skews.
- After generating your IP core, create a Intel® Quartus® Prime project and select your device from the Available devices list.
- To launch the Timing Analyzer, select Timing Analyzer from the Tools menu.
- To run early I/O timing analysis:
- Select Run Tcl Script from the Script menu.
- Run \ip\ed_synth\ed_synth_emif_a10_0\altera_emif_arch_nf_<variation_name>\synth\<variation_name>_report_io_timing.tcl.
The following figure shows an early I/O timing analysis from the Timing Analyzer using a DDR3 example design.
Report DDR details the read capture, write, address and command, DQS gating, and write leveling timing analyses, which are identical to those obtained after a full design compilation. Core FPGA timing paths are not included in early I/O timing analysis.
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