External Memory Interfaces Intel® Arria® 10 FPGA IP User Guide

ID 683106
Date 5/10/2023
Public
Document Table of Contents

4.4.10. caltiming9

address=40(32 bit)

Field Bit High Bit Low Description Access
cfg_t_param_4_act_to_act 7 0 The four-activate window timing parameter. Read

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