External Memory Interfaces Intel® Arria® 10 FPGA IP User Guide

ID 683106
Date 5/10/2023
Public
Document Table of Contents

4.1.1.22. clks_sharing_master_out for DDR3

Core clocks sharing master interface

Table 30.  Interface: clks_sharing_master_outInterface type: Conduit
Port Name Direction Description
clks_sharing_master_out Output This port should fanout to all the core clocks sharing slaves.

Did you find the information on this page useful?

Characters remaining:

Feedback Message