6.4. DDR3 Board Design Guidelines
The following areas are discussed:
- I/O standards
- comparison of various types of termination schemes, and their effects on the signal quality on the receiver
- proper drive strength setting on the FPGA to optimize the signal integrity at the receiver
- effects of different loading types, such as components versus DIMM configuration, on signal quality
DDR3 SDRAM interface signals use one of the following JEDEC* I/O signaling standards:
- SSTL-15—for DDR3.
- SSTL-135—for DDR3L.
It is important to understand the trade-offs between different types of termination schemes, the effects of output drive strengths, and different loading types, so that you can swiftly navigate through the multiple combinations and choose the best possible settings for your designs.
The following key factors affect signal quality at the receiver:
- Leveling and dynamic ODT
- Proper use of termination
- Layout guidelines
As memory interface performance increases, board designers must pay closer attention to the quality of the signal seen at the receiver because poorly transmitted signals can dramatically reduce the overall data-valid margin at the receiver. The following figure shows the differences between an ideal and real signal seen by the receiver.
Terminations and Slew Rates with Intel Arria 10 Devices
Channel Signal Integrity Measurement
Design Layout Guidelines
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