External Memory Interfaces Intel® Arria® 10 FPGA IP User Guide

ID 683106
Date 5/10/2023
Public
Document Table of Contents

3.8. Intel® Arria® 10 EMIF Ping Pong PHY

Ping Pong PHY allows two memory interfaces to share the address and command bus through time multiplexing. Compared to having two independent interfaces that allocate address and command lanes separately, Ping Pong PHY achieves the same throughput with fewer resources, by sharing the address and command lanes.

In Intel® Arria® 10 EMIF, Ping Pong PHY supports both half-rate and quarter-rate interfaces for DDR3, and quarter-rate for DDR4 .

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