External Memory Interfaces Intel® Arria® 10 FPGA IP User Guide

ID 683106
Date 12/19/2023

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

9.4. QDR-IV Board Design Guidelines

The following topics provide guidelines for you to improve your system's signal integrity and layout guidelines to help successfully implement a QDR-IV SRAM interface in your system.

The following topics focus on the following key factors that affect signal integrity:

  • I/O standards
  • QDR-IV SRAM configurations
  • Signal terminations
  • Printed circuit board (PCB) layout guidelines

I/O Standards

QDR-IV SRAM interface signals use one of the following JEDEC* I/O signaling standards:

  • HSTL-15—provides the advantages of lower power and lower emissions.
  • HSTL-18—provides increased noise immunity with slightly greater output voltage swings.