3.4.2. Technical Restrictions
The periodic OCT recalibration engine is enabled only when all of the following criteria are met:
- The memory interface is configured to use the Altera Hard Memory Controller for DDR4.
- The memory interface is configured for either DDR4 UDIMM or component topologies. RDIMM and LRDIMM topologies are not supported.
- The memory interface is not used with the hardened processor subsystem.
- The memory interface does not use Ping-Pong PHY.
- The memory interface does not use calibrated I/O standards for address, command, or clock signals.
- The memory interface uses calibrated I/O standards for the data bus.
- The memory does not use the memory mapped register (MMR) interface of the HMC, including ECC modes.
- You have not explicitly disabled periodic OCT recalibration in the parameter editor.
- The specified device is a production level device (that is, not an ES/ES2/ES3 class device).
Periodic OCT recalibration requires that each EMIF instance in the design employ a dedicated RZQ resistor. Because this restriction cannot be detected at IP generation time, you must explicitly disable the periodic OCT recalibration engine for a given interface if it shares an RZQ resistor with another interface. Ensure that you observe this restriction when automatically upgrading EMIF IP from older versions of the Intel® Quartus® Prime software.
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