External Memory Interfaces Intel® Arria® 10 FPGA IP User Guide

ID 683106
Date 5/10/2023
Public
Document Table of Contents

4.1.4.10. emif_usr_reset_n for QDR II/II+/II+ Xtreme

User clock domain reset interface

Table 113.  Interface: emif_usr_reset_nInterface type: Reset Output
Port Name Direction Description
emif_usr_reset_n Output Reset for the user clock domain. Asynchronous assertion and synchronous deassertion

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