External Memory Interfaces Intel® Arria® 10 FPGA IP User Guide

ID 683106
Date 12/19/2023
Public
Document Table of Contents
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3.2. Intel® Arria® 10 EMIF Sequencer

The EMIF sequencer for Intel® Arria® 10 devices is fully hardened in silicon, with executable code to handle protocols and topologies. Hardened RAM contains the calibration algorithm.

The sequencer is responsible for the following operations:

  • Initializes memory devices.
  • Calibrates the external memory interface.
  • Governs the hand-off of control to the memory controller.
  • Handles recalibration requests and debug requests.
  • Handles all supported protocols and configurations.
Figure 14. EMIF Sequencer Operation