External Memory Interfaces Intel® Arria® 10 FPGA IP User Guide

ID 683106
Date 5/10/2023
Public
Document Table of Contents

4.1.6.17. cal_debug_out_clk for RLDRAM 3

User calibration debug clock interface

Table 168.  Interface: cal_debug_out_clkInterface type: Clock Output
Port Name Direction Description
cal_debug_out_clk Output User clock domain

Did you find the information on this page useful?

Characters remaining:

Feedback Message