1.9.3. Timing-Driven Synthesis Settings
The Intel® Quartus® Prime NativeLink feature allows timing constraints that are applied in the Synplify software to be forward-annotated for the Intel® Quartus® Prime software with an .scf file for timing‑driven place and route.
The Synplify Synthesis Report File (.srr) contains timing reports of estimated place‑and-route delays. The Intel® Quartus® Prime software can perform further optimizations on a post-synthesis netlist from third-party synthesis tools. In addition, designs might contain black boxes or intellectual property (IP) functions that have not been optimized by the third-party synthesis software. Actual timing results are obtained only after the design has been fully placed and routed in the Intel® Quartus® Prime software. For these reasons, the Intel® Quartus® Prime post place-and-route timing reports provide a more accurate representation of the design. Use the statistics in these reports to evaluate design performance.
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