Intel® Quartus® Prime Standard Edition User Guide: Third-party Synthesis

ID 683796
Date 9/24/2018
Document Table of Contents

1.7. Design Constraints Support

You can specify timing constraints and attributes by using the SCOPE window of the Synplify software, by editing the .sdc file, or by defining the compiler directives in the HDL source file. The Synplify software forward-annotates many of these constraints to the Intel® Quartus® Prime software.

After synthesis is complete, do the following steps:

  1. Import the .vqm netlist to the Intel® Quartus® Prime software for place-and-route.
  2. Use the .tcl file generated by the Synplify software to forward‑annotate your project constraints including device selection. The .tcl file calls the generated .scf to forward-annotate Timing Analyzer timing constraints.