Intel® Quartus® Prime Standard Edition User Guide: Third-party Synthesis

ID 683796
Date 9/24/2018
Document Table of Contents Additional Considerations for Compile Points

To ensure that changes to a Compile Point do not affect the top-level parent module, turn off the Update Compile Point Timing Data option in the Implementation Options dialog box. If this option is turned on, updates to a child module can impact the top-level module.

You can apply the syn_allowed_resources attribute to any Compile Point view to restrict the number of resources for a particular module.

When using Compile Points with incremental compilation, be aware of the following restrictions:

  • To use Compile Points effectively, you must provide timing constraints (timing budgeting) for each Compile Point; the more accurate the constraints, the better your results are. Constraints are not automatically budgeted, so manual time budgeting is essential. Intel recommends that you register all inputs and outputs of each partition. This avoids any logic delay penalty on signals that cross-partition boundaries.
  • When using the Synplify attribute syn_useioff to pack registers in the I/O Elements (IOEs) of Intel devices, these registers must be in the top-level module. Otherwise, you must direct the Intel® Quartus® Prime software to perform I/O register packing instead of the syn_useioff attribute. You can use the Fast Input Register or Fast Output Register options, or set I/O timing constraints and turn on Optimize I/O cell register placement for timing on the Advanced Settings (Fitter) dialog box in the Intel® Quartus® Prime software.
  • There is no incremental synthesis support for top-level logic; any logic in the top‑level is resynthesized during every compilation in the Synplify software.

For more information about using Compile Points and setting Synplify attributes and constraints for both top-level and lower-level Compile Points, refer to the Synopsys FPGA Synthesis User Guide and the Synopsys FPGA Synthesis Reference Manual.

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