Intel® Quartus® Prime Standard Edition User Guide: Third-party Synthesis

ID 683796
Date 9/24/2018
Public
Document Table of Contents

2.9.2. Instantiating IP Cores With IP Catalog-Generated VHDL Files

The IP Catalog generates a VHDL component declaration file <output file>.cmp and a VHDL instantiation template file <output file>_inst.vhd for use in your Precision Synthesis design. Incorporate the component declaration and instantiation template into your top-level design to instantiate the IP core wrapper file, <output file>.vhd.

Adding the IP core wrapper file <output file>.vhd in your Precision Synthesis project is optional, but you must add the file to your Intel® Quartus® Prime project along with the Precision Synthesis-generated EDIF or VQM netlist.

Alternatively, you can include the IP core wrapper file <output file>.v in your Precision Synthesis project and turn on the Exclude file from Compile Phase option in the Precision Synthesis software to exclude the file from compilation and to copy the file to the appropriate directory for use by the Intel® Quartus® Prime software during place-and-route.

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