- 2.8.2. Running the Intel® Quartus® Prime Software Manually Using the Precision Synthesis‑Generated Tcl Script
- 22.214.171.124. Creating a Single Intel® Quartus® Prime Project for a Standard Incremental Compilation Flow
1.10.1. Instantiating Intel FPGA IP Cores with the IP Catalog
The Synplify software uses the Intel® Quartus® Prime timing and resource estimation netlist feature to report more accurate resource utilization and timing performance estimates, and uses timing-driven optimization, instead of treating the IP core as a “black box.” Including the generated IP core variation wrapper file in your Synplify project, gives the Synplify software complete information about the IP core.
Verify that the correct Intel® Quartus® Prime version is specified in the Synplify software before compiling the generated file to ensure that the software uses the correct library definitions for the IP core. The Quartus Version setting must match the version of the Intel® Quartus® Prime software used to generate the customized IP core.
In addition, ensure that the QUARTUS_ROOTDIR environment variable specifies the installation directory location of the correct Intel® Quartus® Prime version. The Synplify software uses this information to launch the Intel® Quartus® Prime software in the background. The environment variable setting must match the version of the Intel® Quartus® Prime software used to generate the customized IP core.
Instantiating Intel FPGA IP Cores with IP Catalog Generated Verilog HDL Files
Instantiating Intel FPGA IP Cores with IP Catalog Generated VHDL Files
Changing Synplify’s Default Behavior for Instantiated Intel FPGA IP Cores
Instantiating Intellectual Property with the IP Catalog and Parameter Editor
Instantiating Black Box IP Cores with Generated Verilog HDL Files
Instantiating Black Box IP Cores with Generated VHDL Files
Other Synplify Software Attributes for Creating Black Boxes
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