Intel® Quartus® Prime Standard Edition User Guide: Third-party Synthesis

ID 683796
Date 9/24/2018
Document Table of Contents

1.9. Synplify Optimization Strategies

Combining Synplify software constraints with VHDL and Verilog HDL coding techniques and Intel® Quartus® Prime software options can help you obtain the results that you require.

For more information about applying attributes, refer to the Synopsys FPGA Synthesis Reference Manual.

Did you find the information on this page useful?

Characters remaining:

Feedback Message