Intel® Quartus® Prime Standard Edition User Guide: Third-party Synthesis

ID 683796
Date 9/24/2018
Public
Document Table of Contents

2.8.4.1. create_clock

You can specify a clock in the Precision Synthesis software.

Specifying a Clock Using create_clock

create_clock -name <clock_name> -period <period in ns> \
-waveform {<edge_list>} -domain <ClockDomain> <pin>

The period is specified in units of nanoseconds (ns). If no clock domain is specified, the clock belongs to a default clock domain main. All clocks in the same clock domain are treated as synchronous (related) clocks. If no <clock_name> is provided, the default name virtual_default is used. The <edge_list> sets the rise and fall edges of the clock signal over an entire clock period. The first value in the list is a rising transition, typically the first rising transition after time zero. The waveform can contain any even number of alternating edges, and the edges listed should alternate between rising and falling. The position of any edge can be equal to or greater than zero but must be equal to or less than the clock period.

If -waveform <edge_list> is not specified and -period <period in ns> is specified, the default waveform has a rising edge of 0.0 and a falling edge of <period_value>/2.

The Precision Synthesis software maps the clock constraint to the Timing Analyzer create_clock setting in the Intel® Quartus® Prime software.

The Intel® Quartus® Prime software supports only clock waveforms with two edges in a clock cycle. If the Precision Synthesis software finds a multi-edge clock, it issues an error message when you synthesize your design in the Precision Synthesis software.

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