ID 683796
Date 9/24/2018
Public

## 1.9.5.7. Register Input and Output Delays

Two advanced options, define_reg_input_delay and define_reg_output_delay, can speed up paths feeding a register, or coming from a register, by a specific number of nanoseconds. The Synplify software attempts to meet the global clock frequency goals for a design as well as the individual clock frequency goals (set with the define_clock attribute). You can use these attributes to add a delay to paths feeding into or out of registers to further constrain critical paths. You can slow down a path that is too highly optimized by setting this attributes to a negative number.

The define_reg_input_delay and define_reg_output_delay options are useful to close timing if your design does not meet timing goals, because the routing delay after placement and routing exceeds the delay predicted by the Synplify software. Rerun synthesis using these options, specifying the actual routing delay (from place‑and‑route results) so that the tool can meet the required clock frequency. Synopsys recommends that for best results, do not make these assignments too aggressively. For example, you can increase the routing delay value, but do not also use the full routing delay from the last compilation.

In the SCOPE constraint window, the registers panel contains the following options:

• Register—Specifies the name of the register. If you have initialized a compiled design, select the name from the list.
• Type—Specifies whether the delay is an input or output delay.
• Route—Shrinks the effective period for the constrained registers by the specified value without affecting the clock period that is forward‑annotated to the Intel® Quartus® Prime software.

Use the following Tcl command syntax to specify an input or output register delay in nanoseconds.

### Input and Output Register Delay

define_reg_input_delay {<register>} -route <delay in ns>
define_reg_output_delay {<register>} -route <delay in ns>