Intel® Quartus® Prime Standard Edition User Guide: Third-party Synthesis

ID 683796
Date 9/24/2018
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2.10.1. Creating a Design with Precision RTL Plus Incremental Synthesis

The Precision RTL Plus incremental synthesis flow for Intel® Quartus® Prime incremental compilation uses a partition-based approach to achieve faster design cycle time.

Using the incremental synthesis feature, you can create different netlist files for different partitions of a design hierarchy within one partition implementation, which makes each partition independent of the others in an incremental compilation flow. Only the portions of a design that have been updated must be recompiled during design iterations. You can make changes and resynthesize one partition in a design to create a new netlist without affecting the synthesis results or fitting of other partitions.

The following steps show a general flow for partition-based incremental synthesis with Intel® Quartus® Prime incremental compilation:

  1. Create Verilog HDL or VHDL design files.
  2. Determine which hierarchical blocks you want to treat as separate partitions in your design, and designate the partitions with the incr_partition attribute.
  3. Create a project in the Precision RTL Plus Synthesis software and add the HDL design files to the project.
  4. Enable incremental synthesis in the Precision RTL Plus Synthesis software using one of these methods:
    • Use the Precision RTL Plus Synthesis GUI to turn on Enable Incremental Synthesis.
    • Run the following command in the Transcript Window:
      setup_design -enable_incr_synth
  5. Run the basic Precision Synthesis flow of compilation, synthesis, and place-and-route on your design. In subsequent runs, the Precision RTL Plus Synthesis software processes only the parts of the design that have changed, resulting in a shorter iteration than the initial run. The performance of the unchanged partitions is preserved.

    The Precision RTL Plus Synthesis software sets the netlist types of the unchanged partitions to Post Fit and the changed partitions to Post Synthesis. You can change the netlist type during timing closure in the Intel® Quartus® Prime software to obtain the best QoR.

  6. Import the EDIF or VQM netlist for each partition and the top-level .tcl file into the Intel® Quartus® Prime software, and set up the Intel® Quartus® Prime project to use incremental compilation.
  7. Compile your Intel® Quartus® Prime project.
  8. If you want, you can change the Intel® Quartus® Prime incremental compilation netlist type for a partition with the Design Partitions Window. You can change the Netlist Type to one of the following options:
    • To preserve the previous post‑fit placement results, change the Netlist Type of the partition to Post-Fit.
    • To preserve the previous routing results, set the Fitter Preservation Level of the partition to Placement and Routing.