2.2. Design Flow
- Create Verilog HDL or VHDL design files.
- Create a project in the Precision Synthesis software that contains the HDL files for your design, select your target device, and set global constraints.
- Compile the project in the Precision Synthesis software.
- Add specific timing constraints, optimization attributes, and compiler directives to optimize the design during synthesis. With the design analysis and cross-probing capabilities of the Precision Synthesis software, you can identify and improve circuit area and performance issues using prelayout timing estimates.
Note: For best results, Mentor Graphics recommends specifying constraints that are as close as possible to actual operating requirements. Properly setting clock and I/O constraints, assigning clock domains, and indicating false and multicycle paths guide the synthesis algorithms more accurately toward a suitable solution in the shortest synthesis time.
- Synthesize the project in the Precision Synthesis software.
- Create an Intel® Quartus® Prime project and import the following files generated by the Precision Synthesis software into the Intel® Quartus® Prime project:
Note: If your design uses the Classic Timing Analyzer for timing analysis in the Intel® Quartus® Prime software versions 10.0 and earlier, the Precision Synthesis software generates timing constraints in the Tcl Constraints File (.tcl). If you are using the Intel® Quartus® Prime software versions 10.1 and later, you must use the Timing Analyzer for timing analysis.
- The Verilog Quartus Mapping File ( .vqm) netlist
- Synopsys Design Constraints File (.sdc) for Timing Analyzer constraints
- Tcl Script Files (.tcl) to set up your Intel® Quartus® Prime project and pass constraints
- After obtaining place-and-route results that meet your requirements, configure or program the Intel device.
You can run the Intel® Quartus® Prime software from within the Precision Synthesis software, or run the Precision Synthesis software using the Intel® Quartus® Prime software.
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