Intel® Quartus® Prime Standard Edition User Guide: Third-party Synthesis

ID 683796
Date 9/24/2018
Document Table of Contents

1.6. Synplify Software Generated Files

During synthesis, the Synplify software produces several intermediate and output files.
Table 1.  Synplify Intermediate and Output Files

File Extensions

File Description


Technology-specific netlist in .vqm file format.

A .vqm file is created for all Intel device families supported by the Intel® Quartus® Prime software.

.scf 1

Synopsys Constraint Format file containing timing constraints for the Timing Analyzer.


Forward-annotated constraints file containing constraints and assignments.

A .tcl file for the Intel® Quartus® Prime software is created for all devices. The .tclfile contains the appropriate Tcl commands to create and set up an Intel® Quartus® Prime project and pass placement constraints.


Technology-independent RTL netlist file that can be read only by the Synplify software.


Technology view netlist file.


Assignment and Configurations file for backward compatibility with the MAX+PLUS II software. For devices supported by the MAX+PLUS II software, the MAX+PLUS II assignments are imported from the MAX+PLUS II .acf file.

.srr 2

Synthesis Report file.

1 If your design uses the Classic Timing Analyzer for timing analysis in the Intel® Quartus® Prime software versions 10.0 and earlier, the Synplify software generates timing constraints in the Tcl Constraints File (.tcl). If you are using the Intel® Quartus® Prime software versions 10.1 and later, you must use the Timing Analyzer for timing analysis.
2 This report file includes performance estimates that are often based on pre-place-and-route information. Use the fMAX reported by the Intel® Quartus® Prime software after place-and-route—it is the only reliable source of timing information. This report file includes post-synthesis device resource utilization statistics that might inaccurately predict resource usage after place-and-route. The Synplify software does not account for black box functions nor for logic usage reduction achieved through register packing performed by the Intel® Quartus® Prime software. Register packing combines a single register and look-up table (LUT) into a single logic cell, reducing logic cell utilization below the Synplify software estimate. Use the device utilization reported by the Intel® Quartus® Prime software after place‑and-route.

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