1.1. About Synplify Support 1.2. Design Flow 1.3. Hardware Description Language Support 1.4. Intel Device Family Support 1.5. Tool Setup 1.6. Synplify Software Generated Files 1.7. Design Constraints Support 1.8. Simulation and Formal Verification 1.9. Synplify Optimization Strategies 1.10. Guidelines for Intel FPGA IP Cores and Architecture-Specific Features 1.11. Incremental Compilation and Block-Based Design 1.12. Synopsys Synplify* Support Revision History
22.214.171.124. Instantiating Intel FPGA IP Cores with IP Catalog Generated Verilog HDL Files 126.96.36.199. Instantiating Intel FPGA IP Cores with IP Catalog Generated VHDL Files 188.8.131.52. Changing Synplify’s Default Behavior for Instantiated Intel FPGA IP Cores 184.108.40.206. Instantiating Intellectual Property with the IP Catalog and Parameter Editor 220.127.116.11. Instantiating Black Box IP Cores with Generated Verilog HDL Files 18.104.22.168. Instantiating Black Box IP Cores with Generated VHDL Files 22.214.171.124. Other Synplify Software Attributes for Creating Black Boxes
1.11.1. Design Flow for Incremental Compilation 1.11.2. Creating a Design with Separate Netlist Files for Incremental Compilation 1.11.3. Using MultiPoint Synthesis with Incremental Compilation 1.11.4. Creating Multiple .vqm Files for a Incremental Compilation Flow With Separate Synplify Projects 1.11.5. Performing Incremental Compilation in the Intel® Quartus® Prime Software
2.1. About Precision RTL Synthesis Support 2.2. Design Flow 2.3. Intel Device Family Support 2.4. Precision Synthesis Generated Files 2.5. Creating and Compiling a Project in the Precision Synthesis Software 2.6. Mapping the Precision Synthesis Design 2.7. Synthesizing the Design and Evaluating the Results 2.8. Exporting Designs to the Intel® Quartus® Prime Software Using NativeLink Integration 2.9. Guidelines for Intel FPGA IP Cores and Architecture-Specific Features 2.10. Incremental Compilation and Block-Based Design 2.11. Mentor Graphics Precision* Synthesis Support Revision History
2.8.1. Running the Intel® Quartus® Prime Software from within the Precision Synthesis Software 2.8.2. Running the Intel® Quartus® Prime Software Manually Using the Precision Synthesis‑Generated Tcl Script 2.8.3. Using the Intel® Quartus® Prime Software to Run the Precision Synthesis Software 2.8.4. Passing Constraints to the Intel® Quartus® Prime Software
2.9.1. Instantiating IP Cores With IP Catalog-Generated Verilog HDL Files 2.9.2. Instantiating IP Cores With IP Catalog-Generated VHDL Files 2.9.3. Instantiating Intellectual Property With the IP Catalog and Parameter Editor 2.9.4. Instantiating Black Box IP Functions With Generated Verilog HDL Files 2.9.5. Instantiating Black Box IP Functions With Generated VHDL Files 2.9.6. Inferring Intel FPGA IP Cores from HDL Code
2.10.1. Creating a Design with Precision RTL Plus Incremental Synthesis 2.10.2. Creating Multiple Mapped Netlist Files With Separate Precision Projects or Implementations 2.10.3. Creating Black Boxes to Create Netlists 2.10.4. Creating Intel® Quartus® Prime Projects for Multiple Netlist Files 2.10.5. Hierarchy and Design Considerations
1.11.4. Creating Multiple .vqm Files for a Incremental Compilation Flow With Separate Synplify Projects
2.7.1. Obtaining Accurate Logic Utilization and Timing Analysis Reports
Historically, designers have relied on post-synthesis logic utilization and timing reports to determine the amount of logic their design requires, the size of the device required, and how fast the design runs. However, today’s FPGA devices provide a wide variety of advanced features in addition to basic registers and look-up tables (LUTs). The Intel® Quartus® Prime software has advanced algorithms to take advantage of these features, as well as optimization techniques to increase performance and reduce the amount of logic required for a given design. In addition, designs can contain black boxes and functions that take advantage of specific device features. Because of these advances, synthesis tool reports provide post‑synthesis area and timing estimates, but you should use the place-and-route software to obtain final logic utilization and timing reports.
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