Intel® Quartus® Prime Standard Edition User Guide: Third-party Synthesis

ID 683796
Date 9/24/2018
Document Table of Contents Other Synplify Software Attributes for Creating Black Boxes

Instantiating IP as a black box does not provide visibility into the IP for the synthesis tool. Thus, it does not take full advantage of the synthesis tool's timing-driven optimization. For better timing optimization, especially if the black box does not have registered inputs and outputs, add timing models to black boxes by adding the syn_tpd, syn_tsu, and syn_tco attributes.

Adding Timing Models to Black Boxes in Verilog HDL

module ram32x4(z,d,addr,we,clk);
    /* synthesis syn_black_box syn_tcol="clk->z[3:0]=4.0"
        syn_tsu2="we->clk=3.0" */
    output [3:0]z;
    input we
    input clk

The following additional attributes are supported by the Synplify software to communicate details about the characteristics of the black box module within the HDL code:

  • syn_resources—Specifies the resources used in a particular black box.
  • black_box_pad_pin—Prevents mapping to I/O cells.
  • black_box_tri_pin—Indicates a tri-stated signal.

For more information about applying these attributes, refer to the Synopsys FPGA Synthesis Reference Manual.