Intel® Quartus® Prime Standard Edition User Guide: Third-party Synthesis

ID 683796
Date 9/24/2018
Document Table of Contents Signal Level Attribute

You can control the implementation of individual multipliers by using the syn_multstyle attribute as shown in the following Verilog HDL code (where <signal_name> is the name of the signal ):
<signal_name> /* synthesis syn_multstyle = "logic" */;

The syn_multstyle attribute applies to wires only; it cannot be applied to registers.

Table 3.  DSP Block Attribute Setting in the Synplify Software
Attribute Name Value Description
syn_multstyle lpm_mult LPM function inferred and multipliers implemented in DSP blocks.
logic LPM function not inferred and multipliers implemented as LEs by the Synplify software.
block_mult DSP IP core is inferred and multipliers are mapped directly to DSP block device primitives (for supported devices).

Signal Attributes for Controlling DSP Block Inference in Verilog HDL Code

module mult(a,b,c,r,en);
    input [7:0] a,b;
    output [15:0] r;
    input [15:0] c;
    input en;
    wire [15:0] temp /* synthesis syn_multstyle="logic" */;

    assign temp = a*b;
    assign r = en ? temp : c;

Signal Attributes for Controlling DSP Block Inference in VHDL Code

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity onereg is port (
    r : out std_logic_vector (15 downto 0);
    en : in std_logic;
    a : in std_logic_vector (7 downto 0);
    b : in std_logic_vector (7 downto 0);
    c : in std_logic_vector (15 downto 0);
end onereg;

architecture beh of onereg is
signal temp : std_logic_vector (15 downto 0);
attribute syn_multstyle : string;
attribute syn_multstyle of temp : signal is "logic";

    temp <= a * b;
    r <= temp when en='1' else c;
end beh;