Intel® Quartus® Prime Standard Edition User Guide: Third-party Synthesis

ID 683796
Date 9/24/2018
Public
Document Table of Contents

2.11. Mentor Graphics Precision* Synthesis Support Revision History

Date

Version

Changes

2015.11.02 15.1.0
  • Changed instances of Quartus II to Intel® Quartus® Prime .

June 2014

14.0.0

  • Dita conversion.
  • Removed obsolete devices.
  • Replaced Intel® FPGA IP, MegaWizard, and IP Toolbench content with IP Catalog and Parameter Editor content.

June 2012

12.0.0

  • Removed survey link.

November 2011

10.1.1

  • Template update.
  • Minor editorial changes.

December 2010

10.1.0

  • Changed to new document template.
  • Removed Classic Timing Analyzer support.
  • Added support for . vqm netlist files.
  • Edited the “Creating Intel® Quartus® Prime Projects for Multiple EDIF Files” on page 15–30 section for changes with the incremental compilation flow.
  • Editorial changes.

July 2010

10.0.0

  • Minor updates for the Intel® Quartus® Prime software version 10.0 release

November 2009

9.1.0

  • Minor updates for the Intel® Quartus® Prime software version 9.1 release

March 2009

9.0.0

  • Updated list of supported devices for the Intel® Quartus® Prime software version 9.0 release
  • Chapter 11 was previously Chapter 10 in software version 8.1

November 2008

8.1.0

  • Changed to 8-1/2 x 11 page size
  • Title changed to Mentor Graphics Precision Synthesis Support
  • Updated list of supported devices
  • Added information about the Precision RTL Plus incremental synthesis flow
  • Updated Figure 10-1 to include SystemVerilog
  • Updated “Guidelines for Intel® FPGA IP and Architecture-Specific Features” on page 10–19
  • Updated “Incremental Compilation and Block-Based Design” on page 10–28
  • Added section “Creating Partitions with the incr_partition Attribute” on page 10–29

May 2008

8.0.0

  • Removed Mercury from the list of supported devices
  • Changed Precision version to 2007a update 3
  • Added note for Stratix IV support
  • Renamed “Creating a Project and Compiling the Design” section to “Creating and Compiling a Project in the Precision RTL Synthesis Software”
  • Added information about constraints in the Tcl file
  • Updated document based on the Intel® Quartus® Prime software version 8.0

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