Intel® Quartus® Prime Standard Edition User Guide: Third-party Synthesis

ID 683796
Date 9/24/2018
Public
Document Table of Contents

1.9.5.3. Preserving Nets

During synthesis, the compiler maintains ports, registers, and instantiated components. However, some nets cannot be maintained to create an optimized circuit. Applying the syn_keep directive overrides the optimization of the compiler and preserves the net during synthesis. The syn_keep directive is a Boolean data type value and can be applied to wires (Verilog HDL) and signals (VHDL). Setting the value to true preserves the net through synthesis.

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