Intel® Quartus® Prime Standard Edition User Guide: Third-party Synthesis

ID 683796
Date 9/24/2018
Document Table of Contents

1.2. Design Flow

The following steps describe a basic Intel® Quartus® Prime software design flow using the Synplify software:
  1. Create Verilog HDL (.v) or VHDL (.vhd) design files.
  2. Set up a project in the Synplify software and add the HDL design files for synthesis.
  3. Select a target device and add timing constraints and compiler directives in the Synplify software to help optimize the design during synthesis.
  4. Synthesize the project in the Synplify software.
  5. Create an Intel® Quartus® Prime project and import the following files generated by the Synplify software into the Intel® Quartus® Prime software. Use the following files for placement and routing, and for performance evaluation:
    • Verilog Quartus Mapping File (.vqm) netlist.
    • The Synopsys Constraints Format (.scf) file for Timing Analyzer constraints.
    • The .tcl file to set up your Intel® Quartus® Prime project and pass constraints.
      Note: Alternatively, you can run the Intel® Quartus® Prime software from within the Synplify software.
  6. After obtaining place-and-route results that meet your requirements, configure or program the Intel device.
Figure 1. Recommended Design Flow