Intel® Quartus® Prime Standard Edition User Guide: Third-party Synthesis

ID 683796
Date 9/24/2018
Public
Document Table of Contents

2.8.4.3. set_output_delay

This port-specific output delay constraint is specified in the Precision Synthesis software.

Using the set_output_delay Constraint

set_output_delay {<delay_value> <port_pin_list>} \
-clock <clock_name> -rise -fall -add_delay

This constraint is mapped to the set_output_delay setting in the Intel® Quartus® Prime software.

When the reference clock <clock_name> is not specified, all clocks are assumed to be the reference clocks for this assignment. The output pin name for the assignment can be an output pin name of a time group.

Note: Although the Precision Synthesis software allows you to set output delays on pins inside the design, these constraints are not sent to the Intel® Quartus® Prime software.

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