Intel® Quartus® Prime Standard Edition User Guide: Third-party Synthesis

ID 683796
Date 9/24/2018
Public
Document Table of Contents

1.11.1. Design Flow for Incremental Compilation

The following steps describe the general incremental compilation flow when using these features of the Intel® Quartus® Prime software:
  1. Create Verilog HDL or VHDL design files.
  2. Determine which hierarchical blocks you want to treat as separate partitions in your design.
  3. Set up your design using the MultiPoint synthesis feature or separate projects so that a separate netlist file is created for each design partition.
  4. If using separate projects, disable I/O pad insertion in the implementations for lower-level partitions.
  5. Compile and map each partition in the Synplify software, making constraints as you would in a non-incremental design flow.
  6. Import the .vqm netlist and .tcl file for each partition into the Intel® Quartus® Prime software and set up the Intel® Quartus® Prime project(s) for incremental compilation.
  7. Compile your design in the Intel® Quartus® Prime software and preserve the compilation results with the post-fit netlist in incremental compilation.
  8. When you make design or synthesis optimization changes to part of your design, resynthesize only the partition you modified to generate a new netlist and .tcl file. Do not regenerate netlist files for the unmodified partitions.
  9. Import the new netlist and .tcl file into the Intel® Quartus® Prime software and recompile the design in the Intel® Quartus® Prime software with incremental compilation.

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