Intel® Quartus® Prime Standard Edition User Guide: Third-party Synthesis

ID 683796
Date 9/24/2018
Document Table of Contents

2.8. Exporting Designs to the Intel® Quartus® Prime Software Using NativeLink Integration

The NativeLink feature in the Intel® Quartus® Prime software facilitates the seamless transfer of information between the Intel® Quartus® Prime software and EDA tools, which allows you to run other EDA design entry/synthesis, simulation, and timing analysis tools automatically from within the Intel® Quartus® Prime software.

After a design is synthesized in the Precision Synthesis software, the technology‑mapped design is written to the current implementation directory as an EDIF netlist file, along with a Intel® Quartus® Prime Project Configuration File and a place‑and‑route constraints file. You can use the Project Configuration script, <project name>.tcl, to create and compile a Intel® Quartus® Prime project for your EDIF or VQM netlist. This script makes basic project assignments, such as assigning the target device specified in the Precision Synthesis software. If you select a newer Intel device, the constraints are written in SDC format to the <project name>_ pnr_constraints.sdc file by default, which is used by the Fitter and the Timing Analyzer in the Intel® Quartus® Prime software.

Use the following Precision Synthesis software command before compilation to generate the <project name>_pnr_constraints.sdc:

setup_design -timequest_sdc

With this command, the file is generated after synthesis.

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