Intel® Quartus® Prime Standard Edition User Guide: Third-party Synthesis

ID 683796
Date 9/24/2018
Document Table of Contents

2.10.2. Creating Multiple Mapped Netlist Files With Separate Precision Projects or Implementations

You can manually generate multiple netlist files, which can be VQM or EDIF files, for incremental compilation using black boxes and separate Precision projects or implementations for each design partition. This manual flow is supported in versions of the Precision software that do not include the incremental synthesis feature. You might also use this feature if you perform synthesis in a team-based environment without a top‑level synthesis project that includes all of the lower‑level design blocks.

In the Precision Synthesis software, create a separate implementation, or a separate project, for each lower‑level module and for the top-level design that you want to maintain as a separate netlist file. Implement black box instantiations of lower‑level modules in your top-level implementation or project.

For more information about managing implementations and projects, refer to the Precision RTL Synthesis User’s Manual.

Note: In a standard Intel® Quartus® Prime incremental compilation flow, Precision Synthesis software constraints made on lower‑level modules are not passed to the Intel® Quartus® Prime software. Ensure that appropriate constraints are made in the top-level Precision Synthesis project, or in the Intel® Quartus® Prime project.

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