Intel® Quartus® Prime Standard Edition User Guide: Third-party Synthesis

ID 683796
Date 9/24/2018
Public
Document Table of Contents

1.9.3.1. Clock Frequencies

For single-clock designs, you can specify a global frequency when using the push‑button flow. While this flow is simple and provides good results, it often does not meet the performance requirements for more advanced designs. You can use timing constraints, compiler directives, and other attributes to help optimize the performance of a design. You can enter these attributes and directives directly in the HDL code. Alternatively, you can enter attributes (not directives) into an .sdc file with the SCOPE window in the Synplify software.

Use the SCOPE window to set global frequency requirements for the entire design and individual clock settings. Use the Clocks tab in the SCOPE window to specify frequency (or period), rise times, fall times, duty cycle, and other settings. Assigning individual clock settings, rather than over‑constraining the global frequency, helps the Intel® Quartus® Prime software and the Synplify software achieve the fastest clock frequency for the overall design. The define_clock attribute assigns clock constraints.

Did you find the information on this page useful?

Characters remaining:

Feedback Message