Intel® Quartus® Prime Standard Edition User Guide: Third-party Synthesis

ID 683796
Date 9/24/2018
Document Table of Contents

2.6.3. Assigning Pin Numbers and I/O Settings

The Precision Synthesis software supports assigning device pin numbers, I/O standards, drive strengths, and slew rate settings to top‑level ports of the design. You can set these timing constraints with the set_attribute command, the GUI, or by specifying synthesis attributes in your HDL code. These constraints are forward‑annotated in the <project name>.tcl file that is read by the Intel® Quartus® Prime software during place‑and‑route and do not affect synthesis.

You can use the set_attribute command in the Precision Synthesis software .sdc file to specify pin number constraints, I/O standards, drive strengths, and slow slew‑rate settings. The table below describes the format to use for entries in the Precision Synthesis software constraint file.

Table 5.  Constraint File Settings


Entry Format for Precision Constraint File

Pin number

set_attribute -name PIN_NUMBER -value "<pin number>" -port <port name>

I/O standard

set_attribute -name IOSTANDARD -value "<I/O Standard>" -port <port name>

Drive strength

set_attribute -name DRIVE -value "<drive strength in mA>" -port <port name>

Slew rate

set_attribute -name SLEW -value "TRUE | FALSE" -port <port name>

You also can use synthesis attributes or pragmas in your HDL code to make these assignments.

Verilog HDL Pin Assignment

//pragma attribute clk pin_number P10;

VHDL Pin Assignment

attribute pin_number : string
attribute pin_number of clk : signal is "P10";

You can use the same syntax to assign the I/O standard using the IOSTANDARD attribute, drive strength using the attribute DRIVE, and slew rate using the SLEW attribute.

For more details about attributes and how to set these attributes in your HDL code, refer to the Precision Synthesis Reference Manual.