Visible to Intel only — GUID: mwh1409960047396
Ixiasoft
Visible to Intel only — GUID: mwh1409960047396
Ixiasoft
2.6.3. Assigning Pin Numbers and I/O Settings
You can use the set_attribute command in the Precision Synthesis software .sdc file to specify pin number constraints, I/O standards, drive strengths, and slow slew‑rate settings. The table below describes the format to use for entries in the Precision Synthesis software constraint file.
Constraint |
Entry Format for Precision Constraint File |
---|---|
Pin number |
|
I/O standard |
|
Drive strength |
|
Slew rate |
|
You also can use synthesis attributes or pragmas in your HDL code to make these assignments.
Verilog HDL Pin Assignment
//pragma attribute clk pin_number P10;
VHDL Pin Assignment
attribute pin_number : string
attribute pin_number of clk : signal is "P10";
You can use the same syntax to assign the I/O standard using the IOSTANDARD attribute, drive strength using the attribute DRIVE, and slew rate using the SLEW attribute.
For more details about attributes and how to set these attributes in your HDL code, refer to the Precision Synthesis Reference Manual.
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