2.10.3. Creating Black Boxes to Create Netlists
To create multiple EDIF netlist files for this design, follow these steps:
- Generate a netlist file for module B. Use B.v/.vhd, D.v/.vhd, and E.v/.vhd as the source files.
- Generate a netlist file for module F. Use F.v/.vhd as the source file.
- Generate a top-level netlist file for module A. Use A.v/.vhd and C.v/.vhd as the source files. Ensure that you create black boxes for modules B and F, which were optimized separately in the previous steps.
The goal is to individually synthesize and generate a netlist file for each lower‑level module and then instantiate these modules as black boxes in the top‑level file. You can then synthesize the top-level file to generate the netlist file for the top‑level design. Finally, both the lower‑level and top-level netlist files are provided to your Intel® Quartus® Prime project.
Did you find the information on this page useful?