Intel® Quartus® Prime Standard Edition User Guide: Third-party Synthesis

ID 683796
Date 9/24/2018
Document Table of Contents

2.10.3. Creating Black Boxes to Create Netlists

In the figure below, the top-level partition contains the top-level block in the design (block A) and the logic that is not defined as part of another partition. In this example, the partition for top-level block A also includes the logic in the sub-block C. Because block F is contained in its own partition, it is not treated as part of the top-level partition A. Another separate partition, B, contains the logic in blocks B, D, and E. In a team‑based design, different engineers may work on the logic in different partitions. One netlist is created for the top-level module A and its submodule C, another netlist is created for module B and its submodules D and E, while a third netlist is created for module F.
Figure 10. Partitions in a Hierarchical Design

To create multiple EDIF netlist files for this design, follow these steps:

  1. Generate a netlist file for module B. Use B.v/.vhd, D.v/.vhd, and E.v/.vhd as the source files.
  2. Generate a netlist file for module F. Use F.v/.vhd as the source file.
  3. Generate a top-level netlist file for module A. Use A.v/.vhd and C.v/.vhd as the source files. Ensure that you create black boxes for modules B and F, which were optimized separately in the previous steps.

The goal is to individually synthesize and generate a netlist file for each lower‑level module and then instantiate these modules as black boxes in the top‑level file. You can then synthesize the top-level file to generate the netlist file for the top‑level design. Finally, both the lower‑level and top-level netlist files are provided to your Intel® Quartus® Prime project.

Note: When you make design or synthesis optimization changes to part of your design, resynthesize only the changed partition to generate the new netlist file. Do not resynthesize the implementations or projects for the unchanged partitions.