1.7.2. Passing Timing Analyzer SDC Timing Constraints to the Intel® Quartus® Prime Software
The Synplify-generated .tcl file contains constraints for the Intel® Quartus® Prime software, such as the device specification and any location constraints. Timing constraints are forward‑annotated in the Synopsys Constraints Format (.scf) file.
The following list of Synplify constraints are converted to the equivalent Intel® Quartus® Prime SDC commands and are forward-annotated to the Intel® Quartus® Prime software in the .scffile:
All Synplify constraints described above are mapped to SDC commands for the Timing Analyzer.
For syntax and arguments for these commands, refer to the applicable topic in this manual or refer to Synplify Help. For a list of corresponding commands in the Intel® Quartus® Prime software, refer to the Intel® Quartus® Prime Help.
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