Intel® Quartus® Prime Standard Edition User Guide: Third-party Synthesis

ID 683796
Date 9/24/2018
Document Table of Contents

1.7.2. Passing Timing Analyzer SDC Timing Constraints to the Intel® Quartus® Prime Software

The Timing Analyzer is a powerful ASIC-style timing analysis tool that validates the timing performance of all logic in your design using an industry standard constraints format, Synopsys Design Constraints (.sdc).

The Synplify-generated .tcl file contains constraints for the Intel® Quartus® Prime software, such as the device specification and any location constraints. Timing constraints are forward‑annotated in the Synopsys Constraints Format (.scf) file.

Note: Synopsys recommends that you modify constraints using the SCOPE constraint editor window, rather than using the generated .sdc, .scf, or .tcl file.

The following list of Synplify constraints are converted to the equivalent Intel® Quartus® Prime SDC commands and are forward-annotated to the Intel® Quartus® Prime software in the .scffile:

  • define_clock
  • define_input_delay
  • define_output_delay
  • define_multicycle_path
  • define_false_path

All Synplify constraints described above are mapped to SDC commands for the Timing Analyzer.

For syntax and arguments for these commands, refer to the applicable topic in this manual or refer to Synplify Help. For a list of corresponding commands in the Intel® Quartus® Prime software, refer to the Intel® Quartus® Prime Help.