Intel® Quartus® Prime Standard Edition User Guide: Third-party Synthesis

ID 683796
Date 9/24/2018
Document Table of Contents
Give Feedback Instantiating Intel FPGA IP Cores with IP Catalog Generated VHDL Files

If you turn on the <output file>.cmp and <output file>_inst.vhd options on the parameter editor, the IP Catalog generates a VHDL component declaration file and a VHDL instantiation template file for use in your Synplify design. These files can help you instantiate the IP core variation wrapper file, <output file>.vhd, in your top‑level design. Include the <output file>.vhd in your Synplify project. The Synplify software includes the IP core information in the output .vqm netlist file. You do not need to include the generated IP core variation wrapper file in your Intel® Quartus® Prime project.