2.9.1. Instantiating IP Cores With IP Catalog-Generated Verilog HDL Files
Include the hollow-body black box module declaration <output file>_bb.v in your Precision Synthesis project to describe the port connections of the black box. Adding the IP core wrapper file <output file>.v in your Precision Synthesis project is optional, but you must add it to your Intel® Quartus® Prime project along with the Precision Synthesis generated EDIF or VQM netlist.
Alternatively, you can include the IP core wrapper file <output file>.v in your Precision Synthesis project and turn on the Exclude file from Compile Phase option in the Precision Synthesis software to exclude the file from compilation and to copy the file to the appropriate directory for use by the Intel® Quartus® Prime software during place-and-route.
Did you find the information on this page useful?