Intel® Quartus® Prime Standard Edition User Guide: Third-party Synthesis

ID 683796
Date 9/24/2018
Document Table of Contents Instantiating Intel FPGA IP Cores with IP Catalog Generated Verilog HDL Files

If you turn on the <output file>_inst.v option on the Parameter Editor, the IP Catalog generates a Verilog HDL instantiation template file for use in your Synplify design. The instantiation template file, <output file>_inst.v, helps to instantiate the IP core variation wrapper file, <output file>.v, in your top‑level design. Include the IP core variation wrapper file <output file>.v in your Synplify project. The Synplify software includes the IP core information in the output .vqm netlist file. You do not need to include the generated IP core variation wrapper file in your Intel® Quartus® Prime project.