Intel® Quartus® Prime Standard Edition User Guide: Third-party Synthesis

ID 683796
Date 9/24/2018
Document Table of Contents RAM Initialization

Use the Verilog HDL $readmemb or $readmemh system tasks in your HDL code to initialize RAM memories. The Synplify compiler forward-annotates the initialization values in the .srs (technology-independent RTL netlist) file and the mapper generates the corresponding hexadecimal memory initialization (.hex) file. One .hex file is created for each of the altsyncram IP cores that are inferred in the design. The .hex file is associated with the altsyncram instance in the .vqm file using the init_file attribute.

The examples show how RAM can be initialized through HDL code, and how the corresponding .hex file is generated using Verilog HDL.

Using $readmemb System Task to Initialize an Inferred RAM in Verilog HDL Code

    $readmemb("mem.ini", mem);
always @(posedge clk)
    raddr_reg <= raddr;
        mem[waddr] <= data;

Sample of .vqm Instance Containing Memory Initialization File

altsyncram mem_hex( .wren_a(we),.wren_b(GND),...);

defparam mem_hex.lpm_type = "altsyncram";
defparam mem_hex.operation_mode = "Dual_Port";
defparam mem_hex.init_file = "mem_hex.hex";