The Precision Synthesis software uses timing constraints, based on the industry-standard .sdc file format, to deliver optimal results. Missing timing constraints can result in incomplete timing analysis and might prevent timing errors from being detected. The Precision Synthesis software provides constraint analysis prior to synthesis to ensure that designs are fully and accurately constrained. The <project name>_pnr_constraints.sdc file, which contains timing constraints in .sdc format, is generated in the Intel® Quartus® Prime software.
Note: Because the .sdc file format requires that timing constraints be set relative to defined clocks, you must specify your clock constraints before applying any other timing constraints.
You also can use multicycle path and false path assignments to relax requirements or exclude nodes from timing requirements, which can improve area utilization and allow the software optimizations to focus on the most critical parts of the design.
For details about the syntax of Synopsys Design Constraint commands, refer to the Precision RTL Synthesis User’s Manual and the Precision Synthesis Reference Manual.